Within a computer system, it is often desirable to connect a variety of peripherals to the system bus of the computer itself for communication with the central processing unit and other devices connected to the computer. A variety of bus types may be used, and for any bus it is important to have bus drivers and bus receivers that allow devices to communicate quickly, efficiently and accurately.
FIG. 1 illustrates an embodiment of a computer system 10. Computer system 10 includes a computer 12, a disk drive 14, a tape drive 16, and any number of other peripherals 18 such as card reader units, voice input/output, displays, video input/output, scanners, etc. The computer and peripherals in this example are connected via a Small Computer System Interface (SCSI) bus 20, although a wide variety of other buses may also be used.
Any number of computers or hosts may be present in computer system 10 and be connected to SCSI bus 20. Each computer may also contain a variety of hardware and software. By way of example, computer 12 includes a monitor 30, a motherboard 32, a wide variety of processing hardware and software 34 and an SCSI host adapter card (or interface card) 36. Host adapter card 36 provides an interface between the microcomputer bus of computer 12 located on motherboard 32 and SCSI bus 20.
SCSI is a universal parallel interface standard for connecting disks and other high performance peripherals to microcomputers. However, it should be appreciated that computer system 10 is an example of a system, and other interface standards having characteristics similar to SCSI may also be used in such a computer system. By way of example, an Intelligent Peripheral Interface (IPI) standard is one such other standard.
In one embodiment, SCSI bus 20 is an 8-bit parallel flat cable interface (18 total signals) with hand shakes and protocols for handling multiple hosts and multiple peripherals. It has both a synchronous and an asynchronous mode, and has defined software protocols. In the embodiment shown, the SCSI bus uses differential drivers, although SCSI is also available with single wire drivers. SCSI interface cards (such as card 36) plug into most microcomputer buses including VME and Multibus I and II. In another embodiment, SCSI bus 20 is a 16-bit parallel cable interface (27 total signals). In other embodiments motherboard 32 has SCSI adapter card 36 incorporated into the motherboard itself, and a separate, plug-in adapter card is not needed. SCSI bus 20 is a multi-drop bus typically produced as a flat cable that connects from a computer 12 to any number of peripherals. In this example, disk drive 14, tape drive 16, and other peripherals 18 connect to SCSI bus 20 by tapping into the bus. In other examples, it is possible for any number of peripherals to be inside computer 12 in which case SCSI bus 20 may also be present inside computer 12 also.
Disk drive 14 includes the physical disk drive unit 40 and SCSI controller card 42 and other internal cables and device level interfaces (not shown) for enabling the unit to communicate with computer 12. After connecting to disk drive 14, SCSI bus 20 continues on to connect to tape drive 16. Tape drive 16 includes the physical tape drive 50, SCSI controller card 52, and other internal cables and interfaces (not shown) for communicating with computer 12.
SCSI bus 20 also connects to any number of other peripherals 18. In alternative embodiments of the invention, any of the peripherals shown may eliminate the SCSI controller card by using an "embedded SCSI" architecture in which the SCSI bus becomes also the device level interface. In these peripherals, a cable such as SCSI bus 20 may be connected directly from motherboard 32 of a computer to a peripheral without the need for connecting to an internal controller card.
FIG. 2 shows in greater detail 50 SCSI bus 20 and connections to it from computer 12 and a peripheral 18. SCSI bus 20 may come in a variety of standards. Illustrated here by way of example, is a 16-bit SCSI bus with a variety of its control signals shown. Shown are the signals data0! 52 through data15! 54, parity 56, ACK (acknowledge) 58, REQ (request) 60, and a variety of other control signals 62.
This example illustrates how one value from computer 12 may be transferred via SCSI bus 20 to peripheral 18. It should be appreciated that any number of data or control signals may be transferred back and forth on the SCSI bus. For example, computer 12 has a value 70 that passes through a driver 72 and over an electrical connection 74 to the bus line data15!. At the peripheral end, the signal on bus line data15! is passed by way of an electrical connection 76 to a receiver 78 whereby value 70 is received in peripheral 18. Techniques by which a value may be transmitted by a driver over an SCSI bus to be received by a receiver in another electronic device are well known to those of skill in the art.
FIG. 3 shows in greater detail 80 a prior art technique by which value 70 is transmitted from computer 12 to peripheral 18. FIG. 3 illustrates a proposed SCSI standard known as the ULTRA 2 Specification being proposed by the SPI-2 working group. As in FIG. 2, FIG. 3 shows a value 70 being transmitted by a driver 72 from computer 12 to a receiver 78 in peripheral 18. Because SCSI bus 20 uses a voltage differential technique of transferring information, value 70 is transmitted using a signal line 82 from driver 72 and also using its complement, signal/84. In other words, signal lines 82 and 84 are used to transmit information for bus line data15! 54. In a similar fashion, information for other bus lines is transmitted using two signal lines.
The SCSI bus also uses a bias voltage in the termination at each end of the SCSI bus. The termination bias voltage is used during the arbitration phase of SCSI protocol in order to help determine which devices are asserting which bits on the bus. Without a termination bias voltage, it would be difficult to determine which device is asserting a data bit because bits not being asserted would be floating. To achieve the termination bias voltage, computer 12 includes a voltage source V(A) 86 (for example, 1.5 volts) and a voltage source V(B) 88 (for example, 1.0 volt) which are connected in series using resistors 90 (for example, 270 ohms), resistor 92 (for example, 138 ohms), and resistor 94 (for example, 270 ohms). This termination bias voltage circuit is connected to signal lines 82 and 84 as shown. Thus, point 91 is typically at 1.3 volts due to the termination bias voltage, and point 93 is typically at 1.2 volts due to the termination bias voltage. The termination bias voltage also results in an approximate termination resistance of 110 ohms.
In a similar fashion, peripheral 18 also includes a termination bias voltage. As in computer 12, resistors 95, 96, and 97 connect in series voltages V(A) and V(B). These voltages and resistances may have similar values as for computer 12 and are connected to signal lines 82 and 84 as shown. Also shown in FIG. 3 are multiple bus taps 98 symbolizing the variety of other devices, computers, and peripherals that may also tap onto SCSI bus 50.
One technique for transmitting data over a SCSI bus uses a low-voltage swing differential (LVD) and a low offset voltage, high speed, differential input receiver. The driver for this type of SCSI bus uses an asymmetrical output, where one direction has more drive strength than the other. The reason for this asymmetrical output is because of the termination bias voltage as shown in FIG. 3. One technique for eliminating the termination bias voltage and transmitting data at high speeds using symmetrical drivers and receivers is discussed in U.S. patent application Ser. No. 08/944,903 referenced above.
However, the use of an interface standard such as SCSI can lead to what is termed the "first pulse problem". The first pulse problem is especially noticeable with the data signals and the parity, ACK, and REQ signals of a SCSI bus. The "first pulse problem" can be described as too much attenuation of a signal for its first pulse after a steady state. If a driver maintains a value for several clock cycles, or one of the clock signals on the bus stops for a few cycles (and maintains a constant value), the first pulse after this constant value (when output driver changes state) will not be of good quality. In other words, when the signal finally changes after being in one state for a number of clock pulses (often as few as four pulses), the very next pulse is of poor quality. First pulses of poor quality lead to inaccurate transmission of data and/or control signals.
The first pulse problem is caused by the frequency roll-off or high frequency attenuation characteristics of cables. This attenuation is combined with a last signal level being driven all the way to its maximum limits while the cable is being driven in a constant state. If a cable is driven to a constant state for a long time, it goes to its maximum possible voltage level, then when a high frequency signal starts to run again, it cannot drive the maximum voltage level in the other direction. Thus, the amount of over drive in the other direction is small. A constant high frequency driven in a cable does not experience the first pulse problem in such a dramatic fashion because the signal never goes to its maximum voltage level in either direction.
Various other technologies encode transmission of data so that there are never long periods of time where the signal is not changing. Thus, because signals are constantly changing for these technologies, the first pulse problem is not as prevalent. This encoding takes place primarily in serial data systems. However, other interface standards such as SCSI use parallel data transmission. In a parallel data transmission the encoding of data can be very problematic and is almost never performed. Thus, for interface standards using parallel data transmission (such as SCSI), the first pulse problem exists.
FIG. 4 illustrates a series of pulses 100 for a particular signal coming from a driver of a low-voltage differential (LVD) SCSI bus (for example). The SCSI bus uses a low-voltage swing differential for communication which results in a particular value to be transmitted being represented by the complementary pulses shown. Signal 101 and signal/102 may originate from a driver such as driver 72 of FIG. 3. By convention, signal 101 represents possible pulses occurring on signal line 82, while signal/102 represents the complement of these pulses as might be occurring on signal line 84.
In a steady state, signal and signal/have a difference of about 500 mV 103. This voltage difference for a pair of signals (representing a value to be transmitted over a differential bus) allows the receiver to accurately determine the value to be transmitted. If signal and signal/do not have a great enough voltage differential, then the receiver is unable to determine what value is being transmitted from the driver. Lack of a great enough voltage differential can occur due to the first pulse problem.
For example, as shown in FIG. 4, signal and signal have remained in a constant state until a first pulse 104 occurs. As can be seen from the pulses, at first pulse 104 signal 101 is only able to obtain a voltage level 105 which is far lower than the voltage level that signal/102 had maintained during its steady state. Likewise, signal/102 is only able to reach a voltage level 106 which is far short of the voltage level maintained by signal 101 in its static state. In this example, peaks 105 and 106 at first pulse 104 are only separated by about 100 mV 107. This minimal voltage separation of 100 mV is to be contrasted with the much larger voltage differential of 500 mV before the first pulse occurred. A differential of only 100 mV is not enough to allow a receiver to correctly interpret a signal and causes problems.
After the first pulse, subsequent pulses 108, 110, 112, etc., are able to achieve a much greater voltage differential. As can be seen in FIG. 4, when switching occurs after first pulse 104, signal and signal/are separated by a voltage differential of about 300 mV in their steady states. For example, at third pulse 110, signal 101 is at a higher voltage level than signal/102 and the difference between these voltage levels is about 300 mV. A voltage differential of about 300 mV is enough of a difference for a receiver to determine accurately the value being transmitted by a driver. However, a minimal 100 mV differential 107 separating signal from signal/at first pulse 104 is not enough of a voltage difference for a receiver to accurately determine the value being transmitted. Thus, a first pulse after a constant state on a differential bus is often of unacceptable quality.
A voltage differential driver and receiver may be implemented in a wide variety of fashions. By way of example, FIG. 4 has illustrated one such embodiment of an LVD SCSI bus line in which a difference of 500 mV occurs in a steady state, a difference of 300 mV is adequate for signal transmission, and a voltage difference of 100 mV is inadequate for transmissions. Of course, other voltage levels and differentials may be appropriate with other types of differential drivers and receivers.
Therefore, a technique and apparatus is desired that would remedy this first pulse problem for differential drivers. Such an apparatus would also minimize output driver strength to reduce the amount of power that an integrated circuit must dissipate.